Elements for programming PROM's, EEPROM's and logic arrays have included fuses and transistors. It is also possible to make programmable connections using shortable elements (antifuses). An antifuse is an element which before programming has a high impedance and which upon application of an appropriate voltage changes to a low impedance conductive state. A thin dielectric, such as silicon dioxide between two conductive regions, such as aluminum, can serve as an antifuse, programmable by the current and local high heat which occur when sufficient voltage is applied to cause current to flow through the dielectric.
Two common programmable arrays are shown in FIGS. 1 and 2. In FIG. 1, horizontal row lines R1 through Rn are connected to vertical column lines C1 through Cm through interconnects each comprising a diode and a programmable connector. The programmable connectors of FIG. 1 are antifuses, although fuses are also commonly used in this application. The diodes and antifuses of FIG. 1 are identified by the row and column which they connect. Thus the diode and antifuse which connect row R2 to column C1 are diode R2,C1 and antifuse R2,C1. To program the array of FIG. 1 so that row R2 is connected to column C1, all columns except C1 are brought to a high voltage and all rows except R2 are brought to a low voltage. Row R2 is brought to a high voltage and column C1 is brought to a low voltage. This combination of voltages causes diodes at intersections not including row R1 or Column C1 to be back biased. There is no voltage drop at intersections of column C1 with rows other than R2 and there is no voltage difference at intersections of row R2 with columns other than C1. However, diode R2,C1 is forward biased so that the full voltage difference is experienced by antifuse R2,C1. If the voltage levels are sufficient to program the particular antifuse, antifuse R2,C1 will short out and form a permanent connection between row R2 and column C1 through diode R2,C1. This technique works well for memory arrays. However, the diodes prevent two-way flow of current and thus the above method may be unacceptable for certain programmable logic applications where bidirectional current flow is required.
A second technique, shown in FIG. 2, eliminates the use of diodes, using simply cross point switch connections, and relies on the use of three voltage levels for selecting the intersection to be connected. As shown in FIG. 2, columns C1 through Cm can be connected to rows R1 through Rn by connecting antifuses at the appropriate intersections. An antifuse is indicated by a .sym. at the intersection. As with FIG. 1, the antifuses will be identified by the rows and columns which they connect.
In order to connect column C1 to row R2, all rows and columns except C1 and R2 are brought to an intermediate voltage level. Column C1 is brought to a high voltage level and row R2 is brought to a low voltage level. With this combination, antifuses at intersections not including row R2 or column C1 experience no voltage difference. Antifuses connecting rows except R2 to column C1 experience the voltage difference between the high and intermediate levels. Antifuses connecting columns except C1 to row R2 experience the voltage difference between the intermediate and low levels. If the intermediate voltage level is half way between the high and low voltage levels, the voltage difference experienced by antifuse R2,C1 is twice that of other elements in row R2 or column C1. If the antifuses can be reliably manufactured such that the voltage difference between the high and low voltages is sufficient to short the element and the voltage rise or difference between intermediate and the high or low voltages is not sufficient to short the element, this technique can be used to program an array of connections without having diodes in the signal path, in contrast to the array of FIG. 1.
Note, however, that after programming the first connection, for example R2,C1, row R2 and column C1 can no longer be brought to different voltage levels for future programming. If it is next desirable to connect row R2 to column Cm, both row R2 and column C1 will be brought to a low level, other columns except for columns C1 and Cm will be brought to an intermediate level, and column Cm will be brought to a high level. Thus in order to place the programming voltage on element R2,Cm, half the programming voltage must be placed across all elements in row R2, column Cm and also column C1, except of course for element R2,C1 which is already programmed.
If it is next desirable to connect element Rn,C1 row Rn will be brought low. Column C1 will be brought high thus placing high voltages on row R2 and column Cm which have been previously connected. But this action places a programming voltage not only on element Rn,Ci which is to be programmed but also on element Rn,Cm which is not intended to be programmed.
Structures such as shown in FIG. 1 are preferred for memories, where isolation of elements is provided by the diodes, and where it is not necessary to have bidirectional current flow. Structures such as shown in FIG. 2 are preferred for interconnect lines where bidirectionality is important and lack of isolation can be dealt with. FIG. 3 shows a structure in which isolation is not provided by diodes but is accomplished by dividing the entire array into smaller units for isolation. When the structure of FIG. 3 is to be programmed, transistors in units BR1,1 and BC1,1 can be turned off while programming the antifuses of section 1,1, thus avoiding the possible erroneous programming which would occur if the entire array were interconnected. Similarly, other sections can be isolated for antifuse programming. For operation of the device in which the antifuse array of FIG. 3 is located, isolating transistors such as those in BR1,1 and BC1,1 are turned on so that the array is interconnected as desired.
Further structures and methods for programming antifuses are known. Elgamal et al., in U.S. Pat. No. 4,758,745 describes a structure and method for programming antifuses which, as shown in FIG. 4 (Elgamal FIG. 1B), uses one channel control logic unit 23 for controlling the voltage to be applied to each line in an array. As shown in FIG. 5, (Elgamal FIG. 5, which is described in Elgamal col. 8, starting at line 53), pass transistors 40 are provided in parallel with programmable elements (antifuses) 46. Pass transistors 40 are used as feed through transistors during programming of one of the programmable elements 46. By turning on all transistors in a horizontal channel except the transistor for which an antifuse is to be programmed, a programming voltage can be applied to that antifuse. For example by turning on all transistors in channel 62c except transistor 40, and applying low and high voltages to opposite ends of the channel 62c, it is possible to generate enough voltage across terminals of antifuse 46 to program antifuse 46. Because the programming voltage must be applied through a series of transistors such as transistor 40, the programming current for programming antifuse 46 will be limited by the resistance of the transistors in channel 62c through which the current must flow. Since final resistance of the programmed antifuse depends upon current during programming, the final antifuse resistance is also limited by the resistance of transistors in channel 62c. Further, the arrangement of FIG. 5 is not easily scaled. Since the resistance of a channel such as 62c depends upon the number of transistors in series, if one were to design a set of devices using the principles of FIG. 5, it would be necessary to use different design rules for each device having a different number of transistors in series. If decoders were added midway when scaling to a larger device, so that a programming current was applied through only a set number of transistors in series, the efficiency of having decoding performed entirely at the periphery of the chip would be lost.
Finally, depending upon the number of antifuses to be programmed in one channel and the order in which they are programmed, the final antifuse resistance can vary considerably.